Circuits are commonly constructed on printed circuit boards (PC boards). These circuits are often complex and can include a large number of integrated circuits (ICs), wherein the ICs can be in a wide variety of packages. The number of ICs and variety of packages on a PC board makes the functionality of the IC's and the interconnect between them difficult to test.
In order to test complex PC board circuits, test architectures such as boundary scan tests have been developed and are well known in the art. A boundary scan test connects all of the ICs on the circuit board in a serial register chain, and test equipment then serially scans a predetermined series of bits into the serial register chain, wherein the series of bits contains both control and data information. The control information controls a state machine on each IC that uses registers and the data information to test the board interconnect and the ICs. One of the registers on each IC is a boundary scan register that includes all of the input, output, and input/output ports on the IC. An IEEE standard for this type of test architecture has been developed under committee, and is known as IEEE 1149.1, or JTAG.
For the boundary scan tests to effectively verify a PC board circuit under the IEEE 1149.1 standard, the ICs on the PC board need to include a test architecture that is JTAG compliant. PC board circuit designers make use of a boundary scan description of the test architecture which describes the characteristics of the test access port and boundary scan architecture on each IC. A specific format, known as Boundary Scan Description Language (BSDL), is used as a standard for boundary scan descriptions and is specified in Supplement B of IEEE Standard 1149.1. A BSDL description of a test architecture includes such things as register descriptions, number of ports, control instructions supported, etc. Designing and verifying the functionality and JTAG compliance of the test architecture state machine and registers on an IC is a difficult and time-consuming task. In addition, an error free BSDL description of the test architecture on each IC needs to be generated for use by PC board designers.
Two different types of tests are useful for verifying test architectures on integrated circuits. The first type is useful for design verification prior to fabrication, and allows a designer to quickly isolate errors so that they can be corrected. This first type of test requires a large amount of memory and takes a relatively long time to execute, which is not critical as this testing is normally done using logic simulation, and the test is only run as many times as are necessary to verify and debug the test architecture.
The second type of test is for production testing, where functionality, overall fault coverage, compactness, and speed are important issues as the test will be used on each IC that is produced. This type of test, which is normally used after the device has been fabricated, uses minimal memory and quickly determines if the test architecture on the IC is fully functional. If there is an error, however, this type of test rarely provides much insight as to the source of the error.
Typical prior art techniques for verifying test access port and boundary scan architectures use a single compliance test to exercise the test architecture and are aimed towards production testing. In some cases the single test is directed at testing the controlling state machine. Although this strategy is useful for finding errors that occur in the state machine circuitry, it does not thoroughly test the boundary scan register interface, which is where the majority of errors have been found to occur. In cases where the single test is more thorough and does exercise the boundary scan register interface, this single-test technique is still unable to verify complete functionality of internal nodes within the design, and often does not support logic simulation, or provide feedback as to the source of any errors detected.
Other prior art techniques are aimed towards design verification, and are used to generate logic simulation stimulus for testing the ICs. Although these pre-fabrication techniques can be used to verify the test access port and boundary scan architecture through simulation, the tests necessary to do so are often very complex and time consuming to develop, as they involve many serial bit shifting steps and are dependent on the specific implementation of JTAG being tested. Because the tests are not automatically generated, no automatic checking of the test results is available, and more time and effort must be spent to determine if the output produced is error-free. In addition, this technique does not verify the BSDL description of the test architecture.
All known prior-art techniques require a completed BSDL description of the test architecture to be tested. BSDL descriptions are complex text files that are time consuming to construct using a text editor, and even more effort can be spent updating a BSDL description when a slight change, such as reordering of a few pins, occurs in a design. Thus, the prior-art techniques discussed do not aid in the generation of BSDL descriptions.
Therefore, a need exists for a method that automatically generates self-checking production and logic simulation test vectors, verifies JTAG compliance, aids in the generation and verification of BSDL descriptions for test architectures, and provides feedback for correcting detected errors in either the BSDL description or the test architecture.